Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays
Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays
Tarih
2016
Yazarlar
Morgul, Muhammed Ceylan
Peker, Furkan
Altun, Mustafa
Süreli Yayın başlığı
Süreli Yayın ISSN
Cilt Başlığı
Yayınevi
IEEE
Özet
In this study, we introduce an accurate capacitorresistor model for nano-crossbar arrays that is to be used for
power/delay/area performance analysis and optimization. Although
the proposed model is technology independent, we explicitly show its
applicability for three different nanoarray technologies where each
crosspoint behaves as a diode, a FET, and a four-terminal switch. In
order to find related capacitor and resistor values, we investigate
upper/lower value limits for technology dependent parameters
including doping concentration, nanowire dimension, pitch size, and
layer thickness. We also use different fan-out capacitors to test the
integration capability of these technologies. Comparison between the
proposed model and a conventional simple one, which generally uses
one/two capacitors for each crosspoint, demonstrates the necessity of
using our model in order to accurately calculate power and delay
values. The only exception where both models give approximately
same results is the presence of considerably low valued resistive
connections between switches. However, we show that this is a rare
case for nano-crossbar technologies.
Açıklama
Anahtar kelimeler
Nano-crossbar array,
Circuit modeling,
Performance analysis,
Emerging technologies,
Post-CMOS
Alıntı
Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays. (2016). 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on, VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium On, 437. https://doi.org/10.1109/ISVLSI.2016.100