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Title: Logic synthesis and defect tolerance for memristive crossbar arrays
Tunali, Onur
Altun, Mustafa
Electronics and Communication Engineering
Keywords: Memristors
Logic functions
Logic arrays
Logic design
logic circuits
Issue Date: 23-Apr-2018
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Istanbul Technical University
Citation: O. Tunali and M. Altun, "Logic synthesis and defect tolerance for memristive crossbar arrays," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 425-430. doi: 10.23919/DATE.2018.8342047 , URL:
Abstract: Contrary to abundant memory related studies of memristive crossbar structures, logic oriented applications are only gaining popularity in recent years. In this paper, we study logic synthesis, regarding both two-level and multi level designs, and defect aspects of memristor based crossbar architectures. First, we introduce our two-level and multi-level logic synthesis techniques. We elaborate on advantages and disadvantages of both approaches with experimental results regarding area cost. After that, we devise a defect model in alignment with the conventional stuck-at open and closed paradigm. In addition, we determine the effects of defects to the operational capacity of the crossbar. Furthermore, we propose a preliminary defect tolerant Boolean logic mapping approach. In order to evaluate our approach, we conduct extensive Monte Carlo simulations with industrial benchmarks. Finally, we discuss future directions concerning both existing two-level and prospective multi-level logic designs as well as defect tolerance with area redundancy.
Description: This is a conference paper.
ISSN: 1558-1101
Other Identifiers: 10.23919/DATE.2018.8342047
Appears in Collections:Elektronik ve Haberleşme Mühendisliği

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