Please use this identifier to cite or link to this item: http://hdl.handle.net/11527/18008
Title: Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation
Authors: Tunali, Onur
Morgül, M. Ceylan
Altun, Mustafa
Elektronik ve Haberleşme Mühendisliği
Electronics and Communication Engineering
Keywords: Memristors
Logic functions
Delays
Logic design
Heuristic algorithms
Logic arrays
Logic gates
Issue Date: 2018
Publisher: IEEE
Citation: O. Tunali, M. C. Morgul and M. Altun, "Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation," in IEEE Micro, vol. 38, no. 5, pp. 22-31, Sep./Oct. 2018. doi: 10.1109/MM.2018.053631138
Series/Report no.: Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer (NANOxCOMP)
Abstract: In this paper, we study defect-tolerant logic synthesis of memristor-based crossbar architectures. We propose a hybrid algorithm, combining heuristic and exact algorithms, that achieves perfect tolerance for 10-percent stuck-at open defect rates. Along with defect tolerance, we also consider area, delay, and power costs of the memristor crossbars to elaborate on two-level and multi-level logic designs.
URI: http://hdl.handle.net/11527/18008
https://doi.org/10.1109/MM.2018.053631138
ISSN: 1937-4143
Other Identifiers: Volume 38
Issue 5
Papers 22–31
Appears in Collections:Elektronik ve Haberleşme Mühendisliği

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