Please use this identifier to cite or link to this item: http://hdl.handle.net/11527/18005
Title: A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices
Authors: Aksoy, Levent
Altun, Mustafa
Elektronik ve Haberleşme Mühendisliği
Electronics and Communication Engineering
Keywords: Logic synthesis
Mantık sentezi
Anahtarlama kafesleri
Switching lattices
Issue Date: 2019
Publisher: IEEE
Citation: L. Aksoy and M. Altun, "A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices," 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, 2019, pp. 1637-1642. doi: 10.23919/DATE.2019.8714809
Series/Report no.: Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer (NANOxCOMP)
Abstract: In recent years the realization of a logic function on two-dimensional arrays of four-terminal switches, called switching lattices, has attracted considerable interest. Exact and approximate methods have been proposed for the problem of synthesizing Boolean functions on switching lattices with minimum size, called lattice synthesis (LS) problem. However, the exact method can only handle relatively small instances and the approximate methods may find solutions that are far from the optimum. This paper introduces an approximate algorithm, called JANUS, that formalizes the problem of realizing a logic function on a given lattice, called lattice mapping (LM) problem, as a satisfiability problem and explores the search space of the LS problem in a dichotomic search manner, solving LM problems for possible lattice candidates. This paper also presents three methods to improve the initial upper bound and an efficient way to realize multiple logic functions on a single lattice. Experimental results show that JANUS can find solutions very close to the minimum in a reasonable time and obtain better results than the existing approximate methods. The solutions of JANUS can also be better than those of the exact method, which cannot be determined to be optimal due to the given time limit, where the maximum gain on the number of switches reaches up to 25%.
URI: http://hdl.handle.net/11527/18005
doi: 10.23919/DATE.2019.8714809
Appears in Collections:Elektronik ve Haberleşme Mühendisliği

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